Index: sys/boot/fdt/dts/openblocksa6.dts
===================================================================
--- sys/boot/fdt/dts/openblocksa6.dts	(revision 0)
+++ sys/boot/fdt/dts/openblocksa6.dts	(working copy)
@@ -0,0 +1,313 @@
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Plat'Home OpenBlocks A6 Device Tree Source.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+	model = "mrvl,OpenBlocksA6";
+	compatible = "OpenBlocksA6";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet0;
+		mpp = &MPP;
+		serial0 = &serial0;
+		serial1 = &serial1;
+		soc = &SOC;
+		sram = &SRAM;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "ARM,88FR131";
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x4000>;	// L1, 16K
+			i-cache-size = <0x4000>;	// L1, 16K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x20000000>;		// 512M at 0x0
+	};
+
+	localbus@f1000000 {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "mrvl,lbc";
+
+		/* This reflects CPU decode windows setup. */
+		ranges = <0x0 0x0f 0xf9300000 0x00100000
+			  0x1 0x1e 0xfa000000 0x00100000
+			  0x2 0x1d 0xfa100000 0x02000000
+			  0x3 0x1b 0xfc100000 0x00000400>;
+
+		nor@0,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x00100000>;
+			bank-width = <2>;
+			device-width = <1>;
+		};
+
+		led@1,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "led";
+			reg = <0x1 0x0 0x00100000>;
+		};
+
+		nor@2,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x2 0x0 0x02000000>;
+			bank-width = <2>;
+			device-width = <1>;
+		};
+
+		nand@3,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x3 0x0 0x00100000>;
+			bank-width = <2>;
+			device-width = <1>;
+		};
+	};
+
+	SOC: soc88f6282@f1000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0x0 0xf1000000 0x00100000>;
+		bus-frequency = <0>;
+
+		PIC: pic@20200 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			reg = <0x20200 0x3c>;
+			compatible = "mrvl,pic";
+		};
+
+		timer@20300 {
+			compatible = "mrvl,timer";
+			reg = <0x20300 0x30>;
+			interrupts = <1>;
+			interrupt-parent = <&PIC>;
+			mrvl,has-wdt;
+		};
+
+		MPP: mpp@10000 {
+			#pin-cells = <2>;
+			compatible = "mrvl,mpp";
+			reg = <0x10000 0x34>;
+			pin-count = <50>;
+			pin-map = <
+				0 0x01
+				1 0x01
+				2 0x01
+				3 0x01
+				4 0x01
+				5 0x01
+				6 0x01
+				7 0x00
+				8 0x03
+				9 0x03
+				10 0x03
+				11 0x03
+				12 0x00
+				13 0x03
+				14 0x03
+				15 0x02
+				16 0x02
+				17 0x00
+				18 0x01
+				19 0x01
+				20 0x00
+				21 0x00
+				22 0x00
+				23 0x00
+				24 0x00
+				25 0x00
+				26 0x00
+				27 0x00
+				28 0x00
+				29 0x00
+				30 0x00
+				31 0x00
+				32 0x00
+				33 0x00
+				34 0x00
+				35 0x00
+				36 0x0B
+				37 0x0B
+				38 0x00
+				39 0x00
+				40 0x00
+				41 0x00
+				42 0x00
+				43 0x00
+				44 0x00
+				45 0x00
+				46 0x00
+				47 0x00
+				48 0x00
+				49 0x00 >;
+		};
+
+		GPIO: gpio@10100 {
+			#gpio-cells = <3>;
+			compatible = "mrvl,gpio";
+			reg = <0x10100 0x20>;
+			gpio-controller;
+			interrupts = <35 36 37 38 39 40 41>;
+			interrupt-parent = <&PIC>;
+		};
+
+		rtc@10300 {
+			compatible = "mrvl,rtc";
+			reg = <0x10300 0x08>;
+		};
+
+		twsi@11000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "mrvl,twsi";
+			reg = <0x11000 0x100>;
+			interrupts = <29>;
+			interrupt-parent = <&PIC>;
+		};
+
+		twsi@11100 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "mrvl,twsi";
+			reg = <0x11100 0x100>;
+			interrupts = <32>;
+			interrupt-parent = <&PIC>;
+		};
+
+		enet0: ethernet@72000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			model = "V2";
+			compatible = "mrvl,ge";
+			reg = <0x72000 0x2000>;
+			ranges = <0x0 0x72000 0x2000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <12 13 14 11 46>;
+			interrupt-parent = <&PIC>;
+			phy-handle = <&phy0>;
+
+			mdio@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "mrvl,mdio";
+
+				phy0: ethernet-phy@0 {
+					reg = <0x0>;
+				};
+			};
+		};
+
+		serial0: serial@12000 {
+			compatible = "ns16550";
+			reg = <0x12000 0x20>;
+			reg-shift = <2>;
+			clock-frequency = <0>;
+			interrupts = <33>;
+			interrupt-parent = <&PIC>;
+		};
+
+		serial1: serial@12100 {
+			compatible = "ns16550";
+			reg = <0x12100 0x20>;
+			reg-shift = <2>;
+			clock-frequency = <0>;
+			interrupts = <34>;
+			interrupt-parent = <&PIC>;
+		};
+
+		crypto@30000 {
+			compatible = "mrvl,cesa";
+			reg = <0x30000 0x10000>;
+			interrupts = <22>;
+			interrupt-parent = <&PIC>;
+
+			sram-handle = <&SRAM>;
+		};
+
+		usb@50000 {
+			compatible = "mrvl,usb-ehci", "usb-ehci";
+			reg = <0x50000 0x1000>;
+			interrupts = <48 19>;
+			interrupt-parent = <&PIC>;
+		};
+
+		xor@60000 {
+			compatible = "mrvl,xor";
+			reg = <0x60000 0x1000>;
+			interrupts = <5 6 7 8>;
+			interrupt-parent = <&PIC>;
+		};
+
+		sata@80000 {
+			compatible = "mrvl,sata";
+			reg = <0x80000 0x6000>;
+			interrupts = <21>;
+			interrupt-parent = <&PIC>;
+		};
+	};
+
+	SRAM: sram@fd000000 {
+		compatible = "mrvl,cesa-sram";
+		reg = <0xfd000000 0x00100000>;
+	};
+
+	chosen {
+		stdin = "serial0";
+		stdout = "serial0";
+	};
+};
Index: sys/arm/mv/gpio.c
===================================================================
--- sys/arm/mv/gpio.c	(revision 237988)
+++ sys/arm/mv/gpio.c	(working copy)
@@ -155,7 +155,8 @@
 		sc->pin_num = 32;
 		sc->irq_num = 4;
 
-	} else if (dev_id == MV_DEV_88F6281) {
+	} else if (dev_id == MV_DEV_88F6281 ||
+		   dev_id == MV_DEV_88F6282) {
 		sc->pin_num = 50;
 		sc->irq_num = 7;
 
Index: sys/arm/mv/kirkwood/kirkwood.c
===================================================================
--- sys/arm/mv/kirkwood/kirkwood.c	(revision 237988)
+++ sys/arm/mv/kirkwood/kirkwood.c	(working copy)
@@ -74,6 +74,8 @@
 	soc_id(&dev, &rev);
 	if (dev == MV_DEV_88F6281 && (rev == 2 || rev == 3))
 		return (TCLK_200MHZ);
+	if (dev == MV_DEV_88F6282 && (rev == 0 || rev == 1))
+		return (TCLK_200MHZ);
 
 	return (TCLK_166MHZ);
 }
Index: sys/arm/mv/mvreg.h
===================================================================
--- sys/arm/mv/mvreg.h	(revision 237988)
+++ sys/arm/mv/mvreg.h	(working copy)
@@ -326,6 +326,7 @@
 #define MV_DEV_88F5182		0x5182
 #define MV_DEV_88F5281		0x5281
 #define MV_DEV_88F6281		0x6281
+#define MV_DEV_88F6282		0x6282
 #define MV_DEV_MV78100_Z0	0x6381
 #define MV_DEV_MV78100		0x7810
 
Index: sys/arm/mv/mv_sata.c
===================================================================
--- sys/arm/mv/mv_sata.c	(revision 237988)
+++ sys/arm/mv/mv_sata.c	(working copy)
@@ -197,6 +197,7 @@
 		sc->sc_edma_qlen = 128;
 		break;
 	case MV_DEV_88F6281:
+	case MV_DEV_88F6282:
 	case MV_DEV_MV78100:
 	case MV_DEV_MV78100_Z0:
 		sc->sc_version = 2;
Index: sys/arm/mv/common.c
===================================================================
--- sys/arm/mv/common.c	(revision 237988)
+++ sys/arm/mv/common.c	(working copy)
@@ -254,7 +254,9 @@
 	uint32_t ef = 0;
 
 	soc_id(&dev, &rev);
-	if (dev == MV_DEV_88F6281 || dev == MV_DEV_MV78100_Z0 ||
+	if (dev == MV_DEV_88F6281 ||
+	    dev == MV_DEV_88F6282 ||
+	    dev == MV_DEV_MV78100_Z0 ||
 	    dev == MV_DEV_MV78100)
 		__asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef));
 	else if (dev == MV_DEV_88F5182 || dev == MV_DEV_88F5281)
@@ -354,6 +356,13 @@
 		else if (r == 3)
 			rev = "A1";
 		break;
+	case MV_DEV_88F6282:
+		dev = "Marvell 88F6282";
+		if (r == 0)
+			rev = "A0";
+		else if (r == 1)
+			rev = "A1";
+		break;
 	case MV_DEV_MV78100_Z0:
 		dev = "Marvell MV78100 Z0";
 		break;
@@ -539,6 +548,7 @@
 	if ((dev == MV_DEV_88F5182 && i < 2) ||
 	    (dev == MV_DEV_88F5281 && i < 4) ||
 	    (dev == MV_DEV_88F6281 && i < 4) ||
+	    (dev == MV_DEV_88F6282 && i < 4) ||
 	    (dev == MV_DEV_MV78100 && i < 8) ||
 	    (dev == MV_DEV_MV78100_Z0 && i < 8))
 		return (1);
@@ -1323,7 +1333,7 @@
 	uint32_t dev, rev;
 
 	soc_id(&dev, &rev);
-	if (dev == MV_DEV_88F6281)
+	if (dev == MV_DEV_88F6281 || dev == MV_DEV_88F6282)
 		return (2);
 	else if ((dev == MV_DEV_MV78100) || (dev == MV_DEV_MV78100_Z0))
 		return (1);
Index: sys/arm/mv/ic.c
===================================================================
--- sys/arm/mv/ic.c	(revision 237988)
+++ sys/arm/mv/ic.c	(working copy)
@@ -105,7 +105,9 @@
 	sc->ic_high_regs = 0;
 	sc->ic_error_regs = 0;
 
-	if (dev_id == MV_DEV_88F6281 || dev_id == MV_DEV_MV78100 ||
+	if (dev_id == MV_DEV_88F6281 ||
+	    dev_id == MV_DEV_88F6282 ||
+	    dev_id == MV_DEV_MV78100 ||
 	    dev_id == MV_DEV_MV78100_Z0)
 		sc->ic_high_regs = 1;
 
Index: sys/arm/conf/OPENBLOCKSA6
===================================================================
--- sys/arm/conf/OPENBLOCKSA6	(revision 0)
+++ sys/arm/conf/OPENBLOCKSA6	(working copy)
@@ -0,0 +1,112 @@
+#
+# Custom kernel for Plat'Home OpenBlocks A6.
+#
+# $FreeBSD$
+#
+
+ident		OPENBLOCKSA6
+include		"../mv/kirkwood/std.sheevaplug"
+
+hints		"OPENBLOCKSA6.hints"
+options 	SOC_MV_KIRKWOOD
+makeoptions	MODULES_OVERRIDE=""
+
+#makeoptions	DEBUG=-g		#Build kernel with gdb(1) debug symbols
+makeoptions	WERROR="-Werror"
+
+options 	SCHED_4BSD		#4BSD scheduler
+options 	INET			#InterNETworking
+options 	INET6			#IPv6 communications protocols
+options 	FFS			#Berkeley Fast Filesystem
+options 	SOFTUPDATES		#Enable FFS soft updates support
+options 	UFS_ACL			#Support for access control lists
+options 	UFS_DIRHASH		#Improve performance on big directories
+options 	NFSCL			#New Network Filesystem Client
+options 	NFSD			#New Network Filesystem Server
+options 	NFSLOCKD		#Network Lock Manager
+options 	NFS_ROOT		#NFS usable as /, requires NFSCL
+options 	BOOTP
+options 	BOOTP_NFSROOT
+options 	BOOTP_NFSV3
+options 	BOOTP_WIRED_TO=mge0
+options 	MSDOSFS			#MSDOS Filesystem
+options 	CD9660			#ISO 9660 Filesystem
+options 	PROCFS			#Process filesystem (requires PSEUDOFS)
+options 	PSEUDOFS		#Pseudo-filesystem framework
+options 	GEOM_PART_GPT		#GUID Partition Tables.
+options 	GEOM_RAID		#Soft RAID functionality.
+options 	GEOM_LABEL		#Provides labelization
+options 	SCSI_DELAY=5000		#Delay (in ms) before probing SCSI
+
+# Root fs on USB device
+#options 	ROOTDEVNAME=\"ufs:/dev/da0a\"
+
+options 	SYSVSHM			#SYSV-style shared memory
+options 	SYSVMSG			#SYSV-style message queues
+options 	SYSVSEM			#SYSV-style semaphores
+options 	_KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+options 	MUTEX_NOINLINE
+options 	RWLOCK_NOINLINE
+options 	NO_FFS_SNAPSHOT
+options 	NO_SWAPPING
+
+# Debugging
+options 	ALT_BREAK_TO_DEBUGGER
+options 	DDB
+options 	KDB
+
+# ATA controllers
+device		ahci		# AHCI-compatible SATA controllers
+device		ata		# Legacy ATA/SATA controllers
+options 	ATA_CAM		# Handle legacy controllers with CAM
+options 	ATA_STATIC_ID	# Static device numbering
+
+# ATA/SCSI peripherals
+device		scbus		# SCSI bus (required for ATA/SCSI)
+device		ch		# SCSI media changers
+device		da		# Direct Access (disks)
+device		sa		# Sequential Access (tape etc)
+device		cd		# CD
+device		pass		# Passthrough device (direct ATA/SCSI access)
+device		ses		# Enclosure Services (SES and SAF-TE)
+device		ctl		# CAM Target Layer
+
+# Pseudo devices
+device		random
+device		pty
+device		loop
+device		md		# Memory "disks"
+
+# Serial ports
+device		uart
+
+# Networking
+device		ether
+device		mge			# Marvell Gigabit Ethernet controller
+device		mii
+device		e1000phy
+device		bpf
+options		HZ=1000
+options		DEVICE_POLLING
+device		vlan
+
+# Marvell Cryptographic Engine and Security Accelerator
+device		cesa			# Marvell security engine
+device		crypto
+device		cryptodev
+
+# USB
+options 	USB_DEBUG	# enable debug msgs
+device		usb
+device		ehci
+device		umass
+
+# Flattened Device Tree
+options 	FDT
+options		FDT_DTB_STATIC
+makeoptions	FDT_DTS_FILE=openblocksa6.dts
+
+# I2C (TWSI)
+#device		iic
+device		iicbus
+device		s390
Index: sys/arm/conf/OPENBLOCKSA6.hints
===================================================================
--- sys/arm/conf/OPENBLOCKSA6.hints	(revision 0)
+++ sys/arm/conf/OPENBLOCKSA6.hints	(working copy)
@@ -0,0 +1,2 @@
+hint.s390rtc.0.at="iicbus1"
+hint.s390rtc.0.addr=0x60
Index: sys/conf/files
===================================================================
--- sys/conf/files	(revision 237988)
+++ sys/conf/files	(working copy)
@@ -1146,6 +1146,7 @@
 dev/iicbus/iicsmb.c		optional iicsmb				\
 	dependency	"iicbus_if.h"
 dev/iicbus/pcf8563.c		optional pcf8563
+dev/iicbus/s390.c		optional s390
 dev/iir/iir.c			optional iir
 dev/iir/iir_ctrl.c		optional iir
 dev/iir/iir_pci.c		optional iir pci
Index: sys/dev/cesa/cesa.c
===================================================================
--- sys/dev/cesa/cesa.c	(revision 237988)
+++ sys/dev/cesa/cesa.c	(working copy)
@@ -1009,6 +1009,7 @@
 
 	switch (d) {
 	case MV_DEV_88F6281:
+	case MV_DEV_88F6282:
 		sc->sc_tperr = 0;
 		break;
 	case MV_DEV_MV78100:
Index: sys/dev/iicbus/s390.c
===================================================================
--- sys/dev/iicbus/s390.c	(revision 0)
+++ sys/dev/iicbus/s390.c	(working copy)
@@ -0,0 +1,270 @@
+/*-
+ * Copyright (c) 2012 Yusuke Tanaka
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Driver for Seiko Instruments 35390A Real-time Clock
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/clock.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+
+#include <dev/iicbus/iicbus.h>
+#include <dev/iicbus/iiconf.h>
+
+#include "clock_if.h"
+#include "iicbus_if.h"
+
+#define S390_DEVNAME		"s390rtc"
+#define S390_ADDR		(0x30 << 1)	/* Fixed I2C Slave Address */
+
+/* Registers are encoded into the slave address */
+#define S390_STATUS1		(0 << 1)
+#define S390_STATUS2		(1 << 1)
+#define S390_REALTIME1		(2 << 1)
+#define S390_REALTIME2		(3 << 1)
+#define S390_INT1_1		(4 << 1)
+#define S390_INT1_2		(5 << 1)
+#define S390_CLOCKADJ		(6 << 1)
+#define S390_FREE		(7 << 1)
+
+/* Status1 bits */
+#define S390_ST1_POC		(1 << 7)
+#define S390_ST1_BLD		(1 << 6)
+#define S390_ST1_24H		(1 << 1)
+#define S390_ST1_RESET		(1 << 0)
+
+/* Status2 bits */
+#define S390_ST2_TEST		(1 << 7)
+
+/* Realtime1 data bytes */
+#define S390_RT1_NBYTES		7
+#define S390_RT1_YEAR		0
+#define S390_RT1_MONTH		1
+#define S390_RT1_DAY		2
+#define S390_RT1_WDAY		3
+#define S390_RT1_HOUR		4
+#define S390_RT1_MINUTE		5
+#define S390_RT1_SECOND		6
+
+struct s390rtc_softc {
+	device_t	sc_dev;
+	uint16_t	sc_addr;
+};
+
+static uint8_t
+bitreverse(uint8_t x)
+{
+	static unsigned char nibbletab[16] = {
+		0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15
+	};
+
+	return (nibbletab[x & 15] << 4) | nibbletab[x >> 4];
+}
+
+static int
+s390rtc_read(device_t dev, uint8_t reg, uint8_t *buf, size_t len)
+{
+	struct s390rtc_softc *sc = device_get_softc(dev);
+	struct iic_msg msg[] = {
+		{
+			.slave = sc->sc_addr + reg,
+			.flags = IIC_M_RD,
+			.len = len,
+			.buf = buf,
+		},
+	};
+	int i;
+	int error;
+
+	error = iicbus_transfer(dev, msg, 1);
+	if (error != 0)
+		return (error);
+
+	/* this chip returns each byte in reverse order */
+	for (i = 0; i < len; ++i)
+		buf[i] = bitreverse(buf[i]);
+
+	return (0);
+}
+
+static int
+s390rtc_write(device_t dev, uint8_t reg, uint8_t *buf, size_t len)
+{
+	struct s390rtc_softc *sc = device_get_softc(dev);
+	struct iic_msg msg[] = {
+		{
+			.slave = sc->sc_addr + reg,
+			.flags = IIC_M_WR,
+			.len = len,
+			.buf = buf,
+		},
+	};
+	int i;
+
+	/* this chip expects each byte in reverse order */
+	for (i = 0; i < len; ++i)
+		buf[i] = bitreverse(buf[i]);
+
+	return (iicbus_transfer(dev, msg, 1));
+}
+
+static int
+s390rtc_probe(device_t dev)
+{
+	if (iicbus_get_addr(dev) != S390_ADDR)
+		return (ENXIO);
+
+	device_set_desc(dev, "Seiko Instruments 35390A Real-time Clock");
+	return (BUS_PROBE_SPECIFIC);
+}
+
+static int
+s390rtc_attach(device_t dev)
+{
+	struct s390rtc_softc *sc;
+	uint8_t reg;
+	int error;
+
+	sc = device_get_softc(dev);
+	sc->sc_dev = dev;
+	sc->sc_addr = iicbus_get_addr(dev);
+
+	/* Reset the chip and turn on 24h mode, after power-off or battery. */
+	error = s390rtc_read(dev, S390_STATUS1, &reg, 1);
+	if (error != 0) {
+		device_printf(dev, "%s: cannot read status1 register\n", __func__);
+		return (error);
+	}
+	if (reg & (S390_ST1_POC | S390_ST1_BLD)) {
+		reg |= S390_ST1_24H | S390_ST1_RESET;
+		error = s390rtc_write(dev, S390_STATUS1, &reg, 1);
+		if (error != 0) {
+			device_printf(dev, "%s: cannot initialize\n", __func__);
+			return (error);
+		}
+	}
+
+	/* Disable the test mode, when enabled. */
+	error = s390rtc_read(dev, S390_STATUS2, &reg, 1);
+	if (error != 0) {
+		device_printf(dev, "%s: cannot read status2 register\n", __func__);
+		return (error);
+	}
+	if (reg & S390_ST2_TEST) {
+		reg &= ~S390_ST2_TEST;
+		error = s390rtc_write(dev, S390_STATUS2, &reg, 1);
+		if (error != 0) {
+			device_printf(dev, "%s: cannot disable the test mode\n", __func__);
+			return (error);
+		}
+	}
+
+	clock_register(dev, 1000000);   /* 1 second resolution */
+	return (0);
+}
+
+static int
+s390rtc_gettime(device_t dev, struct timespec *ts)
+{
+	uint8_t bcd[S390_RT1_NBYTES];
+	struct clocktime ct;
+	struct s390rtc_softc *sc;
+	int error;
+
+	sc = device_get_softc(dev);
+	error = s390rtc_read(dev, S390_REALTIME1, bcd, S390_RT1_NBYTES);
+	if (error != 0) {
+		device_printf(dev, "%s: cannot read realtime1 register\n", __func__);
+		return (error);
+	}
+
+	/*
+	 * Convert the register values into something useable.
+	 */
+	ct.nsec = 0;
+	ct.sec = FROMBCD(bcd[S390_RT1_SECOND]);
+	ct.min = FROMBCD(bcd[S390_RT1_MINUTE]);
+	ct.hour = FROMBCD(bcd[S390_RT1_HOUR] & 0x3f);
+	ct.day = FROMBCD(bcd[S390_RT1_DAY]);
+	ct.dow = bcd[S390_RT1_WDAY] & 0x07;
+	ct.mon = FROMBCD(bcd[S390_RT1_MONTH]);
+	ct.year = FROMBCD(bcd[S390_RT1_YEAR]) + 2000;
+
+	return (clock_ct_to_ts(&ct, ts));
+}
+
+static int
+s390rtc_settime(device_t dev, struct timespec *ts)
+{
+	uint8_t bcd[S390_RT1_NBYTES];
+	struct clocktime ct;
+	struct s390rtc_softc *sc;
+
+	sc = device_get_softc(dev);
+	clock_ts_to_ct(ts, &ct);
+
+	/*
+	 * Convert our time representation into something the S-xx390
+	 * can understand.
+	 */
+	bcd[S390_RT1_SECOND] = TOBCD(ct.sec);
+	bcd[S390_RT1_MINUTE] = TOBCD(ct.min);
+	bcd[S390_RT1_HOUR] = TOBCD(ct.hour);
+	bcd[S390_RT1_DAY] = TOBCD(ct.day);
+	bcd[S390_RT1_WDAY] = ct.dow;
+	bcd[S390_RT1_MONTH] = TOBCD(ct.mon);
+	bcd[S390_RT1_YEAR] = TOBCD(ct.year % 100);
+
+	return (s390rtc_write(dev, S390_REALTIME1, bcd, S390_RT1_NBYTES));
+}
+
+static device_method_t s390rtc_methods[] = {
+	DEVMETHOD(device_probe,		s390rtc_probe),
+	DEVMETHOD(device_attach,	s390rtc_attach),
+
+	DEVMETHOD(clock_gettime,	s390rtc_gettime),
+	DEVMETHOD(clock_settime,	s390rtc_settime),
+
+	DEVMETHOD_END
+};
+
+static driver_t s390rtc_driver = {
+	S390_DEVNAME,
+	s390rtc_methods,
+	sizeof(struct s390rtc_softc),
+};
+static devclass_t s390rtc_devclass;
+
+DRIVER_MODULE(s390rtc, iicbus, s390rtc_driver, s390rtc_devclass, NULL, NULL);
+MODULE_VERSION(s390rtc, 1);
+MODULE_DEPEND(s390rtc, iicbus, 1, 1, 1);
Index: sys/dev/mvs/mvs_soc.c
===================================================================
--- sys/dev/mvs/mvs_soc.c	(revision 237988)
+++ sys/dev/mvs/mvs_soc.c	(working copy)
@@ -63,6 +63,7 @@
 } mvs_ids[] = {
 	{MV_DEV_88F5182, 0x00,   "Marvell 88F5182",	2, MVS_Q_GENIIE|MVS_Q_SOC},
 	{MV_DEV_88F6281, 0x00,   "Marvell 88F6281",	2, MVS_Q_GENIIE|MVS_Q_SOC},
+	{MV_DEV_88F6282, 0x00,   "Marvell 88F6282",	2, MVS_Q_GENIIE|MVS_Q_SOC},
 	{MV_DEV_MV78100, 0x00,   "Marvell MV78100",	2, MVS_Q_GENIIE|MVS_Q_SOC},
 	{MV_DEV_MV78100_Z0, 0x00,"Marvell MV78100",	2, MVS_Q_GENIIE|MVS_Q_SOC},
 	{0,              0x00,   NULL,			0, 0}
Index: sys/dev/mge/if_mge.c
===================================================================
--- sys/dev/mge/if_mge.c	(revision 237988)
+++ sys/dev/mge/if_mge.c	(working copy)
@@ -258,7 +258,9 @@
 	uint32_t d, r;
 
 	soc_id(&d, &r);
-	if (d == MV_DEV_88F6281 || d == MV_DEV_MV78100 ||
+	if (d == MV_DEV_88F6281 ||
+	    d == MV_DEV_88F6282 ||
+	    d == MV_DEV_MV78100 ||
 	    d == MV_DEV_MV78100_Z0) {
 		sc->mge_ver = 2;
 		sc->mge_mtu = 0x4e8;
Index: sys/dev/mii/e1000phy.c
===================================================================
--- sys/dev/mii/e1000phy.c	(revision 237988)
+++ sys/dev/mii/e1000phy.c	(working copy)
@@ -106,6 +106,7 @@
 	MII_PHY_DESC(xxMARVELL, E1111),
 	MII_PHY_DESC(xxMARVELL, E1116),
 	MII_PHY_DESC(xxMARVELL, E1116R),
+	MII_PHY_DESC(xxMARVELL, E1116R_29),
 	MII_PHY_DESC(xxMARVELL, E1118),
 	MII_PHY_DESC(xxMARVELL, E1149R),
 	MII_PHY_DESC(xxMARVELL, E3016),
@@ -208,6 +209,7 @@
 		case MII_MODEL_xxMARVELL_E1111:
 		case MII_MODEL_xxMARVELL_E1112:
 		case MII_MODEL_xxMARVELL_E1116:
+		case MII_MODEL_xxMARVELL_E1116R_29:
 		case MII_MODEL_xxMARVELL_E1118:
 		case MII_MODEL_xxMARVELL_E1149:
 		case MII_MODEL_xxMARVELL_E1149R:
@@ -215,7 +217,8 @@
 			/* Disable energy detect mode. */
 			reg &= ~E1000_SCR_EN_DETECT_MASK;
 			reg |= E1000_SCR_AUTO_X_MODE;
-			if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116)
+			if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 ||
+			    sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29) 
 				reg &= ~E1000_SCR_POWER_DOWN;
 			reg |= E1000_SCR_ASSERT_CRS_ON_TX;
 			break;
@@ -243,6 +246,7 @@
 		PHY_WRITE(sc, E1000_SCR, reg);
 
 		if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 ||
+		    sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29 ||
 		    sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149 ||
 		    sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149R) {
 			PHY_WRITE(sc, E1000_EADR, 2);
@@ -259,6 +263,7 @@
 	case MII_MODEL_xxMARVELL_E1118:
 		break;
 	case MII_MODEL_xxMARVELL_E1116:
+	case MII_MODEL_xxMARVELL_E1116R_29:
 		page = PHY_READ(sc, E1000_EADR);
 		/* Select page 3, LED control register. */
 		PHY_WRITE(sc, E1000_EADR, 3);
